Espressif Systems /ESP32-C6 /HINF /CFG_DATA7

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Interpret as CFG_DATA7

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PIN_STATE0CHIP_STATE0 (SDIO_RST)SDIO_RST 0 (SDIO_IOREADY0)SDIO_IOREADY0 0 (SDIO_MEM_PD)SDIO_MEM_PD 0 (ESDIO_DATA1_INT_EN)ESDIO_DATA1_INT_EN 0 (SDIO_SWITCH_VOLT_SW)SDIO_SWITCH_VOLT_SW 0 (DDR50_BLK_LEN_FIX_EN)DDR50_BLK_LEN_FIX_EN 0 (CLK_EN)CLK_EN 0 (SDDR50)SDDR50 0 (SSDR104)SSDR104 0 (SSDR50)SSDR50 0 (SDTD)SDTD 0 (SDTA)SDTA 0 (SDTC)SDTC 0 (SAI)SAI 0 (SDIO_WAKEUP_CLR)SDIO_WAKEUP_CLR

Description

SDIO configuration register

Fields

PIN_STATE

configure cis addr 318 and 574

CHIP_STATE

configure cis addr 312, 315, 568 and 571

SDIO_RST

soft reset control for sdio module

SDIO_IOREADY0

sdio io ready, high enable

SDIO_MEM_PD

sdio memory power down, high active

ESDIO_DATA1_INT_EN

enable sdio interrupt on data1 line

SDIO_SWITCH_VOLT_SW

control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V

DDR50_BLK_LEN_FIX_EN

enable block length to be fixed to 512 bytes in ddr50 mode

CLK_EN

sdio apb clock for configuration force on control:0-gating,1-force on.

SDDR50

configure if support sdr50 mode in cccr

SSDR104

configure if support sdr104 mode in cccr

SSDR50

configure if support ddr50 mode in cccr

SDTD

configure if support driver type D in cccr

SDTA

configure if support driver type A in cccr

SDTC

configure if support driver type C in cccr

SAI

configure if support asynchronous interrupt in cccr

SDIO_WAKEUP_CLR

clear sdio_wake_up signal after the chip wakes up

Links

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