SDIO configuration register
| PIN_STATE | configure cis addr 318 and 574 |
| CHIP_STATE | configure cis addr 312, 315, 568 and 571 |
| SDIO_RST | soft reset control for sdio module |
| SDIO_IOREADY0 | sdio io ready, high enable |
| SDIO_MEM_PD | sdio memory power down, high active |
| ESDIO_DATA1_INT_EN | enable sdio interrupt on data1 line |
| SDIO_SWITCH_VOLT_SW | control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V |
| DDR50_BLK_LEN_FIX_EN | enable block length to be fixed to 512 bytes in ddr50 mode |
| CLK_EN | sdio apb clock for configuration force on control:0-gating,1-force on. |
| SDDR50 | configure if support sdr50 mode in cccr |
| SSDR104 | configure if support sdr104 mode in cccr |
| SSDR50 | configure if support ddr50 mode in cccr |
| SDTD | configure if support driver type D in cccr |
| SDTA | configure if support driver type A in cccr |
| SDTC | configure if support driver type C in cccr |
| SAI | configure if support asynchronous interrupt in cccr |
| SDIO_WAKEUP_CLR | clear sdio_wake_up signal after the chip wakes up |